In currently used transistor-transistor logic (TTL) devices and circuits, logical values corresponding to binary "1" and "0" are ordinarily represented at the output by a high level voltage for example in the range of 2.5 to 5 volts and a low level voltage for example in the range of 0 to 0.8 volts. Such TTL output devices and circuits are described for example in U.S. Pat. No. 4,255,670 for "Transistor Logic Tristate Output With Feedback"; U.S. Pat. No. 4,287,433 for "Transistor Logic Tristate Output With Reduced Power Dissipation"; U.S. Pat. No. 4,311,927 for "Transistor Logic Tristate Device With Reduced Output Capacitance"; U.S. Pat. No. 4,321,490 for "Transistor Logic Output For Reduced Power Consumption and Increased Speed During Low to High Transition"; and U.S. Pat. No. 4,330,723 for "Transistor Logic Output Device For Diversion of Miller Current". Overall the TTL family of logic circuits including the low power Schottky TTL circuits and the Fairchild Advanced Schottky TTL circuits provide a combination of relatively short propagation delays with relatively low power dissipation.
On the other hand, emitter coupled logic (ECL) circuits and devices which may provide higher speed switches, generally operate at negative voltage with the high and low level voltage signals established on either side of a negative reference voltage for example in the range of -1.2 to -2.0 volts. For example with a reference voltage of -1.2 volts, the high level voltage signal is in the range of for example -0.8 volts while the low level voltage signal is in the range of -1.6 volts. For a reference voltage of -2.0 volts, the high level voltage signals may be in the order for example of -1.6 volts with the low level voltage signals in the order of for example -2.4 volts.
The typical TTL output device or TTL internal buffer circuit includes a pull-up transistor element comprising a Darlington transistor pair for sourcing current to the output of the circuit from a high potential source V.sub.cc, typically 5 volts .+-.0.5 volts for providing high level voltage signals. A pull-down transistor element sinks current from the circuit output to low potential typically ground or 0 volts for establishing low level voltage signals at the output. The phase splitter transistor element controls the respective states of the pull-up and pull-down transistor elements in response to data signals at the TTL circuit input.
On the other hand, the typical ECL gate or circuit includes a pair of transistors with common emitter coupling providing alternative transistor collector paths from a high level voltage or high potential at ground or 0 volts. The transistors are operatively coupled for switching current between the collector paths according to input signals at the base of one of the transistors. An ECL current source is coupled between the common emitter coupling and a negative voltage such as -5 volts .+-.0.5 volts for generating current in the alternate transistor collector paths.
One of the ECL gate transistors is selected to be the input signal transistor for receiving ECL input data signals at the base of the input signal transistor. The other transistor constitutes a reference transistor and the negative reference voltage signal typically in the range of -1.2 to -2 volts applied to the base of the reference transistor establishes the high and low voltage level signals in the negative voltage range. The output of the ECL gate or circuit is obtained from the collector nodes of the ECL transistor pair typically through emitter follower buffer transistors which provide current gain and shift the voltage levels. A feature and advantage of the ECL gate or circuit is that complementary output signals are available from the collector nodes. Furthermore, the input signal transistor may comprise multiple parallel transistors for multiple inputs or transistors arranged to provide desired logic functions and combinations. Further description of ECL gates and circuits can be found, for example, in the F100K ECL USER'S HANDBOOK, Copyright 1982, Fairchild Camera and Instrument Corporation, Advanced Bi-polar Division, 441 Whisman Road, Mountain View, Calif. 94042, Chapter 2, "Circuit Basics", and the F100K ECL DATA BOOK, Chapter 1, "Family Overview", by the same publisher.
To obtain the advantages of both ECL and TTL circuits, gates, internal buffers and output devices, translators are required for translating the logic data signals from the voltage levels of one logic circuit family to voltage levels compatible with the other. Such an ECL to TTL translator according to the prior art is illustrated in FIG. 1. Generally the conventional ECL to TTL translator 10 comprises an ECL input gate G1 for receiving ECL voltage level logic input signals ECL V.sub.in at the input 12 compatible with ECL circuits and a TTL output gate G2 for delivering corresponding TTL voltage level logic output signals TTL V.sub.out at the output 14 compatible with TTL circuits. The ECL input gate G1 includes a pair of transistors Q1 and Q2 with the common emitter coupling 15 providing alternate transistor collector paths 16 and 18. The collector resistor RL1 indicated by a rectangle symbol in the transistor collector path 16 of transistor Q1 establishes the low level voltage at the collector node of transistor Q1. The ECL current source I1 generates the switching source current also designated I1 through either of the alternate collector paths 16 and 18 according to the conducting state of transistors Q1 and Q2.
The current source I1 is connected between the common emitter node 15 and the low level voltage source V.sub.ee which may be, for example -5 volts .+-.0.5 volts, and is typically a transistor current source for generating a source current I1 through either transistor in the range of for example 0.15 to 1 MA. The reference voltage V.sub.ref applied to the base node of transistor Q2 is selected to establish the relative high level and low level voltages for the ECL data signals in the negative voltage range.
To provide translation of the ECL input data signals at input 12 to TTL voltage levels, a TTL output gate is coupled to ground. The TTL output gate transistor Q3 is coupled through collector resistor RL3 to a high level TTL voltage source V.sub.cc in the order of +5 volts .+-.0.5 volts, typical of TTL circuits, rather than a V.sub.cc level of ground voltage or 0 volts used with ECL gates. A ground voltage coupling 20 at the emitter node of transistor Q3 and the collector node of transistor Q2 defines the low voltage end of the positive voltage range for the TTL output voltage level signals.
ECL voltage level input signals ECL V.sub.in at the input 12 of ECL gate G1 operate the ECL gate in the conventional manner for switching the source current between the collector paths 16 and 18. In the ECL to TTL translator, however, the collector resistor RL1 is selected to provide sufficient base drive to the TTL output gate transistor Q3 when the transistor Q1 is not conducting so that Q3 remains conducting and TTL low level voltage signals appears at the output 14. Thus, a low level ECL voltage level signal at the input 12 below the reference voltage V.sub.ref turns off Q1 and switches the source current to the transistor collector path 18 of then conducting transistor Q2. The TTL output transistor Q3 also becomes conducting and a TTL low level voltage output signal in the positive range above ground or zero voltage appears at the output 14.
On the other hand, a high level ECL voltage input signal in the negative range just below ground or zero volts at the input 12 above the reference voltage V.sub.ref drives transistor Q1 to conduction and the source current I1 switches to the transistor collector path 16 of transistor Q1. The TTL output gate transistor Q3 is deprived of base drive current and turns off so that a high level TTL voltage output signal appears at the output 14. Collector resistor RL3 is selected to provide the desired TTL high voltage level at the output 14 in the positive voltage range.
In the prior art translator of FIG. 1, the current available to turn off the TTL output gate transistor Q3 is limited to the source current I1. This source current for the ECL input gate is small compared to the transient current during turn-on of an equivalent TTL active pull-down transistor element. The source current I1 for the ECL input gate G1 is limited to a level small enough not to saturate the ECL gate G1, typically in the range of 0.15 to 1 mA. A comparatively long turn-off time for transistor Q3 is therefore required in the conventional translator 10 of FIG. 1, especially at elevated temperatures. Because of the limitation on the size of the source current I1, accelerated turn-off of TTL output gate transistor Q3 by increasing the source current discharging the base of the TTL pull-down transistor element Q3 is not possible.
Furthermore, the voltage swing for separation between the ECL high level and low level voltages in the negative range on either side of the reference voltage at ECL gate G1 must be relatively large to maintain TTL output gate transistor Q3 in the nonconducting or off condition in the presence of transient variation in the ground potential or "ground bounce". Such ground bounce is experienced in the translator 10 as a large transient change in the high or low level voltage sources V.sub.cc and/or V.sub.ee, particularly if there are many outputs coupled to the same translator chip. The large voltage swing or separation between the high and low level voltages in the negative range of the ECL input gate G1 results in long and variable propagation delays across the translator. Provision for variation of the source current I1 in order to track variations in the high and low level boundary voltage sources V.sub.cc and V.sub.ee provides only limited improvement.
Another prior art ECL to TTL translator for use with TTL tristate output devices and buffers is illustrated in FIG. 2. The ECL to tristate TTL translator 30 is similar to the translator of FIG. 1 in that it includes the ECL input gate G1 for receiving ECL voltage level logic input signals ECL V.sub.in at the input 12 and a TTL output gate G2 for delivering corresponding TTL voltage level logic output signals TTL V.sub.out at the translator output 14. In this example, however, the TTL output gate G2 is a tristate output device or buffer circuit 35 of the type, for example described in U.S. Pat. No. 4,255,670. In the prior art example of FIG. 2, however, the tristate enable circuitry which turns off the transistor elements of the device for enabling the high impedance third state has been omitted for clarity.
Such a TTL tristate device includes dual phase splitter transistors Q3 and Q4, one of which, transistor Q3, alone controls the pull-up transistor element of the tristate device for isolating the enable gate circuitry from the output. The other phase splitter transistor Q4 is coupled at its collector node to the output 14 through feedback diode D1 to accelerate sinking of current from the output to ground potential node 20 through the pull-down transistor element Q8 during transition at the output from high to low potential. The tristate device or circuit 35 also includes a so-called "AC Miller Killer" 25 for diverting and actively discharging Miller feedback current at the base of the pull-down transistor element to ground during transition from low to high level potential at the output 14. Such "AC Miller Killer" circuits are described, for example, in U.S. Pat. Nos. 4,321,490 and 4,330,723 assigned to the common assignee of the present invention.
An additional disadvantage of the ECL to tristate TTL translator 30 of FIG. 2 beyond the problems of the translator 20 of FIG. 1 is that the dual phase splitter transistors Q3 and Q4, because of the common base and common emitter couplings in current mirror configuration, exhibit "current hogging". As feedback current from the signal output 14 through feedback diode D1 to the collector of phase splitter transistor Q4 accelerates sinking of current from the signal output to low potential during transition at the signal output from high to low potential, the emitter currents of phase splitter transistors Q3 and Q4 tend to equalize because of the current mirror coupling configuration. As a result, phase splitter transistor Q3 pre-empts and "hogs" the base drive current from transistor Q4 destroying the .beta..sup.2 amplification of sinking current otherwise achieved through the pull-down transistor element Q8 as a result of the feedback circuit through diode D1. This considerably reduces the effectiveness of the output feedback diode D1 in accelerating sinking current and curtailing transmission line reflections.
In the example of FIG. 2 it should be noted that the ECL voltage level signal input 12 is applied at the base of ECL gate transistor Q2 rather than transistor Q1. The dual phase splitter transistors Q3 and Q4 provide first and second TTL transistor collector paths 19a and 19b through respective collector resistors RL3 and RL4 indicated by rectangles coupled in parallel. The reference voltage V.sub.ref is applied to the base of transistor Q1, in this instance the reference transistor.